An LDO regulator allows providing a stable output voltage in spite of fluctuations in the general supply voltage of the circuit in which it is installed.
When a circuit containing an LDO regulator is powered up, or when there is an accidental short circuit of the regulator output, it is necessary to limit the output current to avoid malfunctions.
In order to limit this short circuit current, one can consider the use of dedicated current-limiting circuits. These circuits would consist of a feedback loop which measures the output current of the regulator, then compares it to a reference current in order to act on the regulator when the output current becomes greater than the reference current.
Such a current-limiting circuit is shown in FIG. 1.
In this circuit, one can see two particular functional units. The first unit REGUL1 represents the voltage regulating loop of the regulator. This regulating loop allows maintaining a stable output voltage Vout. The second unit LIMIT1 represents the current-limiting loop.
In what follows, only the current-limiting loop is considered. A person skilled in the art is able to understand the operation of the regulating loop when reading the circuit.
In order to access the output current Iout, a PMOS copy transistor T10 is arranged such that it copies the output current issuing from the PMOS power transistor T11.
In order to simplify the presentation, the current from the transistor T11 almost entirely flows to the output, so for practical means it is the output current. The current drawn by the resistors of the regulating loop is negligible compared to the current issuing from the transistor.
The transistors T10 and T11 are paired transistors on silicon and are arranged such that the gate of T10 is connected to the gate of T11, and the source of T10 is connected to the source of T11.
Thus the drain current Imirror of the transistor T10 is proportional to the drain current Iout of the transistor T11.
The transistors T10 and T11 have the same physical properties. In particular, they have the same gate length L. However, they have different gate widths W10 and W11. In fact, the width W11 of the gate of T11 is much greater than the width W10 of the gate of T10.
Thus by using the linear model for MOS transistors, we have:
      I    out    =                    W        11                    W        10              ·                  I        mirror            .      
The drain of the transistor T10 is coupled to the non-inverting input of a comparator COMP1 as well as to a resistor R10. The inverting input of the comparator is coupled to a reference current source Iref in parallel with a second resistor R11. The two resistors R10 and R11 each have a grounded end. For example, they have the same R value.
Thus the output Vs10 of the comparator COMP1 is a voltage proportional to the difference between the current Imirror (which is proportional to the output current Iout) and the reference current Iref. The coefficient of proportionality is the product of the resistor R and the gain G10 of the comparator.
The output from the comparator is coupled to the gates of the PMOS transistors T10 and T11. Thus, using the small signal model, the current Iout is proportional to the voltage output from the comparator, with the coefficient of proportionality being the gain Gmp of the transistor T11.
One can therefore model the signals in the following manner:Vs10=G10·R·(Imirror−Iref)Iout=−Gmp·Vs10.
Lastly one can express Iout as a function of Iref, using:
      I    out    =                    w        11                    w        10              ⁢                                        G                          m              ⁢                                                          ⁢              p                                ·                      G            10                    ·          R                                                    G                              m                ⁢                                                                  ⁢                p                                      ·                          G              10                        ·            R                    +          1                    ·                        I          ref                .            
As the open-loop gain Gmp·G10·R is very high, one can simplify the expression for Iout as follows:
      I    out    =                    w        11                    w        10              ·                  I        ref            .      
One can therefore see that it is possible to set the output current, through the choice of the values for Iref and W10.
The current consumption is very high in this current-limiting loop. In addition, this consumption grows even greater as the size of the power transistor T11 decreases.
A few values are given below to illustrate this.
TABLE 1Current consumed by the comparator COMP1Iad = 4 μAOutput currentIout = 200 mAReference currentIref = 1 μAWidth of gate of transistor T11W11 = 32 000 μmWidth of gate of transistor T10W10 = 10 μmLength of gate of transistors T10 and T11L = 0.2 μm
The current Iq consumed by the current-limiting loop can be approximated by adding the reference current, the mirror current, and the current consumed by the comparator:Iq=Iref+Iad+Imirror 
which is:
      I    q    =            I      ref        +          I      ad        +                            W          10                          W          11                    ⁢                        I          0                .            
Using the numbers in the above table, one obtains a current Iq=67.5 μA.
The specifications for LDO regulators impose a current consumption of less than 150 μA. The current-limiting loop therefore already consumes close to half of the objective.
In order to reduce this consumption, one can reduce W10. However, the topography of the circuit does not allow much reduction in this parameter. One can also consider increasing W11. However, there is almost no room for adjustment here because the output current depends on W11.
In addition, the accuracy of the current-limiting loop is very low because the pairing of the transistors T10 and T11 is made difficult by their difference in surface area which can have a ratio as high as 2000 or more.
FIG. 2 illustrates the topography of these transistors in the LDO circuit. One can see that it is difficult to pair these two transistors because almost the entire surface area of the silicon is occupied by T11.
The precision of the current-limiting loop can be estimated in comparison to the accuracy of the copying of the current by the transistor T10. The standard deviation is calculated on the relative error in the recopying of the current, and the accuracy of the recopying is estimated as six times this standard deviation. Then the accuracy is expressed as:
      acc    =          6      ·                                                  4              ·                                                A                  vt                  2                                                  V                  gt                  2                                                      +                          A              β              2                                            2            ·                          W              10                        ·            L                                ,where Vgt: the difference in voltage between the gate and the source of the transistor T10 on the one hand and the threshold voltage of the transistor on the other, and Avt and Aβ: parameters of the circuit.
The accuracy was calculated for several circuits with the same parameters and for different values of W10, L, and Vgt.
The results are presented in the following table.
TABLE 2CircuitAvt (mV · μm)Aβ (% · μm)W10 (μm)L(μm)Vgt (mV)Acc19.40.032100.62000.2429.40.032150.63670.1239.40.032100.62070.2349.40.03250.64340.1859.40.032200.61900.2369.40.032100.61800.27
The accuracy ranges from 12% to 27%. This level of accuracy is low, and does not take into account the effects of temperature and voltage offsets. When such phenomena are taken into account, the result is an even lower accuracy.